Optimizing PCB Layout
نویسنده
چکیده
eGaN FETs are available in a Wafer Level Chip-Scale Package (WLCSP) with terminals in a Land Grid Array (LGA) format. Some of these devices do not offer a separate gate-return source pin, but rather a number of very low inductance LGA solder bars as shown in figure 1. These parts can be treated in the same way as one provided with a dedicated gate return pin or bar, by allocating the source pads closest to the gate to act as the “star” connection point for both the gate loop and power loop. The layout of the gate and power loops are then separated by having the currents flow in opposite or orthogonal directions as shown in figure 1
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